Sentris

Thermal Emission Microscope for Semiconductor Device Fault Isolation


Defect Depth




Determining fault depth in 3 dimensional system-in-package (3D SiP) devices is becoming increasingly important due to their expanding complexity and decreasing dimensions. As the number of stacked die in 3D SiP devices grows, isolating the root cause of defects within the package becomes more challenging. Sentris provides a proven, non-destructive technique to localize the depth of faults through 3D SiP packages.


Phase Angle

Phase angle represents the time delay between powering a device and subsequent heating on the surface of a device. Phase angle can be used to determine the depth of a fault inside a device. The amount of time delay, or phase angle, is dependent on the thermal conductance of the device and defect depth.

Phase angle is measured in units of degrees and has a range of 0° to -360°. A phase angle close to 0° is an indication of heating occurring immediately after powerup, typically taking place on or near the surface of the device. Negative phase angle values, such as -120°, indicates heating occurring at some time after powerup, taking place beneath the surface of the device. Larger values of phase angle indicate heating occurriing at even greater depths.


Phase Lag

For thermally conductive materials such as bare semiconductor die correctly bonded to a conductive substrate, the measured phase angle of heat sources located on the surface of the die will be very close to 0°. This is due to the very close tracking of surface temperature with applied power. For thermally non-conductive materials such as plastics, however, the measured phase angle of surface heat sources will be less than 0° but greater than -90°. This is due to the lag in surface temperature compared with applied power. It is important to keep in mind that phase lag can be caused by heat source depth, as well as material thermal conductivity.


3D SiP Construction

3D SiP devices are complex structures comprised of multiple stacked semiconductor die, die-attach adhesive, and package mold compound. Modelling the thermal diffusion and phase relationships of heat originating from defect sites using thermal simulation software is very difficult. The thermal properties of die, adhesive, and mold compound are often not known precisely and the interfaces between these materials makes the problem even more complex. For these reasons, it is usually more effective to correlate phase angle to fault depth experimentally.


Calculating Defect Depth

By measuring the phase angle of one or more known reference heat sources inside a device, a relationship between phase angle and depth can be plotted. This plot can then be used to estimate the depth of unkown faults by comparing their phase angle to the plot.

The relationship between phase angle and depth is dependent on the cycle frequency of the lock-in test. A suitable frequency should be selected that results in a high plot slope. This will enable differentiation between different die levels more clearly. Standard procedure is to first test a device at a moderate frequency, such as 2.5Hz. Then, depending on the phase results of this test, another test may be conducted at a higher or lower frequency. If the phase results are between 0° and -140°, for example, the next test should be performed at a higher frequency, such as 3.75Hz. On the other hand, if the phase angle is between -220° and -360°, the next test should be performed at a lower frequency, such as 1.25Hz. If the phase is between -140° and -220°, the test frequency does not need to be changed.

To create a defect depth plot, the device must be tested by cycling power to at least one reference heat source whose depth is known. Defective devices can be used by recording the phase angle of known faults at various depths. Internal I/O diodes located on multiple die levels can also be used as reference heat sources by forward biasing them.


 


Applying Power

The applied voltage level is generally set so that approximately 1-5 mW is dissipated within the defect. This level of power is generally sufficient to localize the fault within seconds or minutes and yet minimize material heating. Large temperature changes within semiconductors can alter their thermal diffusion properties and modify the phase/depth relationship.

Many 3D SiP devices undergo an initialization process that is triggered at a specific voltage level. If the applied voltage is cycled between 0 and a value above the initialization voltage level, the initialization process may cause non-defect related power dissipation that can interfere with detecting the true fail site. In these cases, the device should be initialized before the lock-in test begins, and the applied voltage should be cycled between two voltages that are above the initialization voltage.

Additionally, some 3D SiP devices include on-chip voltage regulators and defect power dissipation may not correlate with on-off power cycling. In these cases, device test equipment may need to be synchronized with the lock-in cycles in order to activate fail sites.



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